As electrical system designs advance and become more complex, it can become more difficult to obtain electrical system analysis tools having an ability to handle all types of modules. Typical computer aided analysis tools at the system/logic analysis level may not have all of the semiconductor or system intellectual property cores and/or library macros to address each aspect within the realm of circuit and/or system level configurations.
To meet the needs for expanding system complexity and enhanced system analysis, tool designers may seek to improve intellectual property core sets and library macrocells. They may seek to improve their analysis capabilities in order to service the more sophisticated demands of potential customers. Sometimes, they may prefer to enhance their analysis capabilities to facilitate hardware design and verification by evolving alternative uses from their existing structures and macros.
The increased levels of integration have enabled greater complexities for systems, such as System-On-Chips (SoC), Digital Signal Processors (DSP), embedded systems, and field-programmable-gate-array (FPGA) based solutions at a board level. Most of these systems may incorporate bi-directional busses and data-routing links. Additionally, they may employ tri-state buffer devices. For example, a typical microprocessor system may use a PCI, ISA, or VME bus, or another bus architecture at the system level for connecting to a number of different elements. Typically, such busses are bi-directional to enable data-routing in either forward or reverse directions.
Some system-level analysis tools, however, may have difficulty handling propagation of signals in both directions as may be required for simulating operation of bi-directional busses. These tools may also have difficulty simulating bi-directional operation between busses and tap interconnects, which may be associated with peripheral components along the bus. In some instances, e.g., where a receiver may also be defined to allow for transmission as well, asynchronous loop hazards may be present within the system level analysis tool.